2-D Systolic Array architecture of CBNS based Discrete Hilbert Transform Processor

Abstract This paper proposes an optimized design of Discrete Hilbert Transform (DHT) processor using Complex Binary Number System (CBNS). The conventional implementation of DHT based on the “divide and conquer” approach involves two separate computational units for the real and imaginary parts, which requires a large silicon area and increases the path delay. In contrast, incorporation of CBNS in transformation techniques facilitates complex-valued signal processing through a single computational unit. The CBNS-DHT processor has been designed using the standard computational method of Fast Fourier Transform (FFT). The 2-D Systolic Array architecture along with a novel processing element has been proposed for CBNS based Complex-valued FFT (CFFT) and Inverse FFT (CIFFT) computations. The architecture of CBNS-CFFT/CIFFT has been extended to develop the CBNS-DHT processor on the Zynq-7000 family, XC7Z020-CLG484 FPGA platform. A comparative performance analysis of CBNS-DHT and Normal Binary Number System (NBNS)-DHT highlights the efficiency of CBNS-DHT in terms of VLSI parameters - silicon area, path-delay and memory utilization. CBNS-CFFT shows significant improvement in path delay and area consumption as compared to NBNS-CFFT for both Twiddle Factors and FFT size, which proves that CBNS based CFFT and DHT processor design is more efficient in terms of speed and area requirements.

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