Z-axis interconnections for high density processors, Part 1

Three-dimensional packaging has been considered by many the best path towards smaller, lighter, faster and less expensive electronics; however, interconnections and efficient thermal transfer have been stumbling blocks towards achieving that goal. Focusing on one of these challenges, this paper examines commercially available z-axis interconnection media, with advantages, disadvantages and selection criteria for the intended system. After an initial down selection based on published data, several connector styles will be tested for life cycle integrity and overall effectiveness for system integration. The primary specifications for the z-axis interconnections are 0.5-mm pitch, area array, high reliability in harsh military environments, and minimal contact force to simplify the external compression structure. This paper also describes the critical nature of the overall structural design and tolerance control, for reliable assemblies and continuous operation; with over two thousand interconnects between each of the five layers in the 3D stack-up.