A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.25-/spl mu/m, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm/sup 2/ silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test.

[1]  Kunihiko Yamaguchi,et al.  High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

[2]  William J. Grundmann,et al.  Designing high performance CMOS microprocessors using full custom techniques , 1997, DAC.

[3]  J. Raskin,et al.  Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling , 1998 .

[4]  J.G. Fossum,et al.  Kink-free SOI analog circuit design with floating-body/NFD MOSFETs , 1997, IEEE Electron Device Letters.

[5]  L. Wagner,et al.  Transient pass-transistor leakage current in SOI MOSFET's , 1997, IEEE Electron Device Letters.

[6]  A. Jakubowski,et al.  Modeling of SOI-MOS capacitors C-V behavior: partially- and fully-depleted cases , 1998 .

[7]  O. Faynot,et al.  Subthreshold kinks in fully depleted SOI MOSFET's , 1995, IEEE Electron Device Letters.

[8]  William J. Bowhill,et al.  Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU , 1995, Digit. Tech. J..

[9]  Jean-Pierre Colinge,et al.  Fully-depleted SOI CMOS for analog applications , 1998 .

[10]  Ching-Te Chuang,et al.  SOI for digital CMOS VLSI: design considerations and advances , 1998, Proc. IEEE.

[11]  Sorin Cristoloveanu,et al.  Noise contribution of the body resistance in partially-depleted SOI MOSFETs , 1998 .

[12]  John Alderman,et al.  Interpretation of capacitance-voltage characteristics on silicon-on-insulator (SOI) capacitors , 1989 .

[13]  S. Li,et al.  Determination of the fixed oxide charge and interface trap densities for buried oxide layers formed by oxygen implantation , 1988 .

[14]  Gilbert Wolrich,et al.  A 300-MHz 64-b quad-issue CMOS RISC microprocessor , 1995 .

[15]  S. C. Kuehne,et al.  SOI MOSFET with buried body strap by wafer bonding , 1998 .

[16]  Ching-Te Chuang,et al.  Floating-body effects in partially depleted SOI CMOS circuits , 1997 .

[17]  John H. Edmondson,et al.  Superscalar instruction execution in the 21164 Alpha microprocessor , 1995, IEEE Micro.

[18]  J. Woo,et al.  Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices , 1998 .

[19]  P. Bannon,et al.  A 433 MHz 64 b quad issue RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[20]  Robert Fox,et al.  A physics-based, dynamic thermal impedance model for SOI MOSFET's , 1997 .

[21]  Yuan Taur,et al.  Design and performance considerations for sub-0.1 /spl mu/m double-gate SOI MOSFET'S , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[22]  Ruben W. Castelino,et al.  Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor , 1995, Digit. Tech. J..

[23]  Yuichi Kado,et al.  Suppression of parasitic bipolar action in ultra-thin-film fully-depleted CMOS/SIMOX devices by Ar-ion implantation into source/drain regions , 1998 .

[24]  Kunihiko Yamaguchi,et al.  High-current small-parasitic-capacitance MOSFET on a poly-Si interlayered (PSI:/spl Psi/) SOI wafer , 1998 .