Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
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B. Parvais | S. Biesemans | T. Schram | T. Kauerauf | L.-A. Ragnarsson | E. Rohr | P. Absil | T. Conard | T. Schram | L. Ragnarsson | B. Parvais | T. Hoffmann | P. Absil | T. Kauerauf | T. Conard | S. Biesemans | E. Rohr | Y. Okuno | M. Cho | J. Tseng | Z. Li | J. Tseng | Y. Okuno | T.Y. Hoffmann | M.J. Cho | Z. Li
[1] R. Degraeve,et al. Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions , 2006, IEEE Transactions on Electron Devices.