A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

A 14.025 Gb/s multi-media transceiver employs on-die Rx AC coupling with baseline wander correction and equalizes up to 26 dB insertion loss at 14.025 Gb/s with a linear equalizer, 10-tap DFE, and 4-tap Tx FIR filter in SST driver. The proposed techniques enable direct feedback for 1st-tap ISI cancellation, and positions of four DFE taps to be adapted over the range of 7 to 38 UI. The prototype is realized in 40 nm CMOS, consumes 410 mW at worst case, and has passed 16GFC compliance tests at 14.025 Gb/s.

[1]  Steve Howard,et al.  AC-coupling strategy for high-speed transceivers of 10Gbps and beyond , 2007, 2007 IFIP International Conference on Very Large Scale Integration.

[2]  V. Gupta,et al.  A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels , 2005, IEEE Journal of Solid-State Circuits.

[3]  Weixin Gai,et al.  A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control , 2009, IEEE Journal of Solid-State Circuits.

[4]  Thomas Toifl,et al.  A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$16 dB Return Loss Over 10 GHz Bandwidth , 2008, IEEE Journal of Solid-State Circuits.

[5]  Yoichi Koyanagi,et al.  A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Pervez M. Aziz,et al.  Adaptation algorithms for a class of continuous time analog equalizers with application to serial links , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[7]  Koichi Yamaguchi,et al.  A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[8]  Jared Zerbe,et al.  A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  S. Gowda,et al.  A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[10]  J.D.H. Alexander.  Clock recovery from random binary signals , 1975 .