Energy-guided exploration of on-chip network design for exa-scale computing

Designing energy-efficient systems under tight performance and energy constraints becomes increasingly challenging for exascale computing. In particular, interconnecting hundreds of cores, caches, integrated memory and I/O controllers in energy efficient way stands out as a new challenge. This paper proposes hierarchical on-chip networks that take the proximity advantage between the cores in smaller clusters as a promising approach toward energy-efficient high performance computing. The design trade-offs of hierarchical interconnect architectures are studied using a fast and scalable design space exploration tool for exascale systems with number of cores in the order of thousands. In particular, we consider a system with 720 processing nodes and two-level network hierarchy. By supporting both traditional cache-based memory model and scratch pad memory (SPM) model, the target system architecture proves to be a good testbed for energy-guided exploration of hierarchical networks.

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