论文信息 - Instruction set architecture scheme for multiple fixed-width instruction sets and conditional execution

Instruction set architecture scheme for multiple fixed-width instruction sets and conditional execution

An instruction set architecture scheme (ISA scheme) is proposed for multiple fixed-width instruction sets in embedded RISC processor. The ISA scheme can achieve efficient ISA change in instruction level. Besides, compared to current conditional execution methods, the parallel conditional execution (PCE) supported by ISA scheme has smaller code size and shorter execution cycle.

[1] Bill Appelbe,et al. High-performance extendable instruction set computing , 2001, Proceedings 6th Australasian Computer Systems Architecture Conference. ACSAC 2001.

[2] B. Appelbe,et al. High-performance extendable instruction set computing , 2001 .

[3] Rajiv Gupta,et al. Enhancing the performance of 16-bit code using augmenting instructions , 2003, LCTES.

[4] Donald S. Fussell,et al. 16-bit vs. 32-bit instructions for pipelined microprocessors , 1993, ISCA '93.