论文信息 - A low-power high-precision tunable WINNER-TAKE-ALL network

A low-power high-precision tunable WINNER-TAKE-ALL network

This paper describes a low power CMOS circuit for selecting the greatest of n analog voltages within a tunable selection range. An increasing speed-decreasing precision law is used to determine the amplitude of the selection range. 16 mV to 4 mV resolution, over a 2 V to 4 V dynamic input range, can be obtained by reducing the speed from 2 MHz to 500 kHz. 1 /spl mu/A quiescent current, 2 /spl mu/A AC current for the selected cells and small size make this circuit available for VLSI implementations of massively parallel analog computational circuits.

Roberto Canegallo | Mauro Chinosi | Alan Kramer

[1] Kiichi Urahama,et al. K-winners-take-all circuit with O(N) complexity , 1995, IEEE Trans. Neural Networks.

[2] John Lazzaro,et al. Winner-Take-All Networks of O(N) Complexity , 1988, NIPS.

[3] Ugur Cilingiroglu. A charge-based neural Hamming classifier , 1993 .

[4] A. Dingwall,et al. An 8-MHz CMOS subranging 8-bit A/D converter , 1985, IEEE Journal of Solid-State Circuits.

[5] M. Degrauwe,et al. Class AB CMOS amplifier micropower SC filters , 1981 .

[6] Yaser S. Abu-Mostafa,et al. On the K-Winners-Take-All Network , 1988, NIPS.

[7] Gabor C. Temes. Simple formula for estimation of minimum clock-feedthrough error voltage , 1986 .

[8] V. A. Pedroni. Inhibitory mechanism analysis of complexity O(N) MOS winner-take-all networks , 1995 .