Candidate subcircuits for functional module identification in logic circuits

Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

[1]  Ronald C. Stogdill Dealing with Obsolete Parts , 1999, IEEE Des. Test Comput..

[2]  Travis E. Doom,et al.  Identifying high-level components in combinational circuits , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[3]  John P. Hayes,et al.  Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering , 1999, IEEE Des. Test Comput..

[4]  A. Chowdhary,et al.  A general approach for regularity extraction in datapath circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[5]  Michael Boehner,et al.  LOGEX-an automatic logic extractor from transistor to gate level for CMOS technology , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[6]  Sandip Kundu GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Christoph M. Hoffmann,et al.  Group-Theoretic Algorithms and Graph Isomorphism , 1982, Lecture Notes in Computer Science.

[8]  Georg Pelz,et al.  Circuit comparison by hierarchical pattern matching , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[9]  Carl Ebeling,et al.  SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[10]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[11]  G. H. Chisholm,et al.  Identification of functional components in combinational circuits , 1998 .

[12]  Murray P. Rosenthal,et al.  Understanding integrated circuits , 1975 .