Monolithic ESD protection for distributed high speed applications in 28-nm CMOS technology

A monolithic electrostatic discharge (ESD) input/output (IO) cell with multi-discharge paths is introduced. This protection cell is demonstrated in a 28 nm high-k metal-gate CMOS technology. The cell is formed as an integral part of the circuit interface, synthesized with IO circuit components for in-situ protection in emerging high speed data rate signal processing systems-on-a-chip (SoCs). At the low IO operating voltage for these CMOS communication applications (<; 0.9 V), the protection cell rapidly actives complementary discharge paths during the different ESD stress modes at the IO (<; 100 ps), for achieving ESD robustness and low standing leakage at the highest circuit operation temperature (<; 10 nA at 125 C).

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