Using Graph-Based CSP to Solve the Address Translation Problem
暂无分享,去创建一个
[1] Andrei Tatarnikov,et al. An Approach to Test Program Generation Based on Formal Specifications of Caching and Address Translation Mechanisms , 2015 .
[2] Daniel J. Sorin,et al. Specifying and dynamically verifying address translation-aware memory consistency , 2010, ASPLOS 2010.
[3] Michael Veksler,et al. Assumption-Based Pruning in Conditional CSP , 2005, CP.
[4] Allon Adir,et al. DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.
[5] Brian Falkenhainer,et al. Dynamic Constraint Satisfaction Problems , 1990, AAAI.
[6] Yves Deville,et al. CP(Graph): Introducing a Graph Computation Domain in Constraint Programming , 2005, CP.
[7] E. V. Kornykhin,et al. Generation of test data for verification of caching mechanisms and address translation in microprocessors , 2010, Programming and Computer Software.
[8] Vitali Sokhin,et al. Threadmill: A post-silicon exerciser for multi-threaded processors , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[9] Eugene C. Freuder,et al. Greater Efficiency for Conditional Constraint Satisfaction , 2003, CP.
[10] Eric Bourreau,et al. Conception d'une contrainte globale de chemin , 2004 .
[11] Subbarao Kambhampati,et al. Planning as constraint satisfaction: Solving the planning graph by compiling it into CSP , 2001, Artif. Intell..
[12] Allon Adir,et al. DeepTrans - a model-based approach to functional verification of address translation mechanisms , 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.
[13] Jean-Guillaume Fages,et al. On the use of graphs within constraint-programming , 2014, Constraints.
[14] Jean-Charles Régin,et al. Robust and Parallel Solving of a Network Design Problem , 2002, CP.
[15] Allon Adir,et al. Genesys-Pro: innovations in test program generation for functional processor verification , 2004, IEEE Design & Test of Computers.
[16] Yehuda Naveh,et al. Constraint-Based Random Stimuli Generation for Hardware Verification , 2006, AI Mag..