Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation
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K. Ishibashi | T. Iwamatsu | T. Hiramoto | H. Shinohara | H. Oda | T. Mizutani | H. Makiyama | N. Sugii | Y. Yamaguchi | K. Ishibashi | T. Hiramoto | T. Iwamatsu | H. Oda | T. Mizutani | H. Makiyama | N. Sugii | Y. Yamamoto | H. Shinohara | Y. Yamaguchi | Y. Yamamoto