论文信息 - FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1M bit FRAM

FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1M bit FRAM

A new FRAM cell design with high immunity to fatigue and imprint has been proposed to achieve a megabit class FRAM with 1T1C cell structure, which has been applied to a 1M bit FRAM operated from a 3 V supply with 1T1C cell structure, 0.5 /spl mu/m rule and 3 /spl mu/m/sup 2/ capacitor area. The simulation result and imprint data predict a lifetime improved 7 orders longer than the conventional scheme.

[1] S. Tanaka,et al. A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor , 2000, IEEE Journal of Solid-State Circuits.

[2] Lee,et al. Computationally Efficient Ferroelectric Capacitor Model For Circuit Simulation , 1997, 1997 Symposium on VLSI Technology.

[3] Wayne I. Kinney. Signal magnitudes in high density ferroelectric memories , 1994 .

[4] Toshiyuki Honda,et al. 2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell , 1997 .

[5] T. Mihara,et al. Evaluation of Imprint Properties in Sol-Gel Ferroelectric Pb(ZrTi)O3 Thin-Film Capacitors , 1993 .

[6] R. Moazzami,et al. A ferroelectric DRAM cell for high density NVRAMs , 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

[7] W. Kraus,et al. A 42.5 mm/sup 2/ 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability , 1998, Seventh Biennial IEEE International Nonvolatile Memory Technology Conference. Proceedings (Cat. No.98EX141).