A DELAYFAULTMODELFORAT-SPEED FAULTSIMULATIONAND TESTGENERATION

We describe a transition fault model, whichiseasyto simulate undertest sequences that areapplied at-speed, andprovides atarget forthegeneration ofat-speed test sequences. At-speed test application allows acircuit tobe tested underitsnormaloperation conditions. However, fault simulation andtest generation fortheexisting fault modelsbecomesignificantly morecomplex duetothe needtohandle faulty signal-transitions that spanmultiple clockcycles. Theproposed fault modelalleviates this shortcoming byintroducing unspecified values intothe faulty circuit whenfault effects mayoccur. Fault detection potentially occurs whenanunspecified valuereaches a primaryoutput. Due to theuncertainty thatan unspecified value propagated toaprimary output will be different fromthefault freevalue, aninherent requirementinthis modelisthatafault wouldbepotentially detected multiple times inorder toincrease thelikelihood ofdetection. Experimental results demonstrate thatthe modelbehaves asexpected interms offault coverage and numbers ofdetections oftarget faults. A variation ofan n-detection test generation procedure forstuck-at faults is used forgenerating test sequences under this model.