Complexity of Matrix Product on a Class of Orthogonally Connected Systolic Arrays

This correspondence studies the time complexity of the parallel computation of the product C = A.B of two dense square matrices A, B of order n, on a class of rectangular orthogonally connected systolic arrays, which are the two-dimensional extensions of the classical pipeline scheme. Such arrays are composed of multiply-add cells without local memory, and, as C is computed, the coefficients cij move vertically, whereas aik and bkj move horizontally in opposite directions. We first introduce a combinatorial formulation of the problem. Then we show that, if the cycle-time of a multiply-add cell is taken as time unit, and if T(p, m) denotes the running time of an optimal algorithm associated with an array of size p x m, then Minpm T(p,m) = 3n -2, and the minimum value of p.m for which this bound is tight is n.n [resp. n(n + 1)] if n is odd (resp. even). When compared to the algorithms previously proposed for the class of arrays based on cells without local memory, the solutions exhibited here appear to be the best, because they are the only ones which run in time T < = 3n -2 on a network of size S < = n(n + 1).

[1]  H. T. Kung,et al.  Systolic (VLSI) arrays for relational database operations , 1980, SIGMOD '80.

[2]  H. Kung,et al.  An algebra for VLSI algorithm design , 1983 .

[3]  Dan I. Moldovan,et al.  On the Analysis and Synthesis of VLSI Algorithms , 1982, IEEE Transactions on Computers.

[4]  Franco P. Preparata,et al.  Area-Time Optimal VLSI Networks for Multiplying Matrices , 1980, Inf. Process. Lett..

[5]  H. T. Kung,et al.  Systolic Arrays for (VLSI). , 1978 .

[6]  H. T. Kung Why systolic architectures? , 1982, Computer.

[7]  Charles E. Leiserson,et al.  Optimizing synchronous systems , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[8]  Benjamin W. Wah,et al.  The Design of Optimal Systolic Arrays , 1985, IEEE Transactions on Computers.

[9]  H. T. Kung,et al.  Direct VLSI Implementation of Combinatorial Algorithms , 1979 .

[10]  Yasunori Dohi,et al.  Design of the PSC: a programmable systolic chip , 1983 .