IC/IP Piracy Assessment of Reversible Logic

Reversible logic is a building block for adiabatic and quantum computing in addition to other applications. Since common functions are non-reversible, one needs to embed them into proper-size reversible functions by adding ancillary inputs and garbage outputs. We explore the Intellectual Property (IP) piracy of reversible circuits. The number of embeddings of regular functions in a reversible function and the percent of leaked ancillary inputs measure the difficulty of recovering the embedded function. To illustrate the key concepts, we study reversible logic circuits designed using reversible logic synthesis tools based on Binary Decision Diagrams and Quantum Multi-valued Decision Diagrams.

[1]  Ramesh Karri,et al.  On Improving the Security of Logic Locking , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Tad Hogg,et al.  Evaluating the friction of rotary joints in molecular machines , 2017, 1701.08202.

[3]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[4]  Robert Wille,et al.  On the Difficulty of Inserting Trojans in Reversible Computing Architectures , 2017, IEEE Transactions on Emerging Topics in Computing.

[5]  M. Pecht,et al.  Bogus: electronic manufacturing and consumers confront a rising tide of counterfeit electronics , 2006, IEEE Spectrum.

[6]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[7]  Robert Wille,et al.  Make it reversible: Efficient embedding of non-reversible functions , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[8]  Robert Wille,et al.  Taking one-to-one mappings for granted: Advanced logic design of encoder circuits , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[9]  Robert Wille,et al.  QMDDs: Efficient Quantum Function Representation and Manipulation , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  M. Thornton,et al.  ESOP-based Toffoli Gate Cascade Generation , 2007, 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[11]  CHARLES RICHTER.  The Future of Computing Depends on Making It Reversible , 2017 .

[12]  I. Chuang,et al.  Quantum Computation and Quantum Information: Introduction to the Tenth Anniversary Edition , 2010 .

[13]  Jeyavijayan Rajendran,et al.  Security analysis of integrated circuit camouflaging , 2013, CCS.

[14]  Tad Hogg,et al.  Mechanical Computing Systems Using Only Links and Rotary Joints , 2018, Journal of Mechanisms and Robotics.

[15]  Jeyavijayan Rajendran,et al.  Activation of logic encrypted chips: Pre-test or post-test? , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[16]  Robert Wille,et al.  Exploiting reversible logic design for implementing adiabatic circuits , 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

[17]  Robert Wille,et al.  Synthesis of approximate coders for on-chip interconnects using reversible logic , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[18]  Robert Wille,et al.  RevLib: An Online Resource for Reversible Functions and Reversible Circuits , 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

[19]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[20]  Kevin D. Osborn,et al.  Ballistic Reversible Gates Matched to Bit Storage: Plans for an Efficient CNOT Gate Using Fluxons , 2018, RC.

[21]  Siddharth Garg,et al.  Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism , 2017, ArXiv.

[22]  Jeyavijayan Rajendran,et al.  VLSI testing based security metric for IC camouflaging , 2013, 2013 IEEE International Test Conference (ITC).

[23]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[24]  Robert Wille,et al.  Automatic design of low-power encoders using reversible circuit synthesis , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Robert Wille,et al.  ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

[26]  Jarrod A. Roy,et al.  Ending Piracy of Integrated Circuits , 2010, Computer.

[27]  Robert Wille,et al.  Synthesis of reversible circuits with minimal lines for large functions , 2012, 17th Asia and South Pacific Design Automation Conference.

[28]  Jarrod A. Roy,et al.  EPIC: Ending Piracy of Integrated Circuits , 2008, 2008 Design, Automation and Test in Europe.

[29]  R Cuykendall,et al.  Reversible optical computing circuits. , 1987, Optics letters.

[30]  Jeyavijayan Rajendran,et al.  Fault Analysis-Based Logic Encryption , 2015, IEEE Transactions on Computers.

[31]  Robert Wille,et al.  One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Gerhard W. Dueck,et al.  A transformation based algorithm for reversible logic synthesis , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[33]  N. Ranganathan,et al.  Mach-Zehnder interferometer based design of all optical reversible binary adder , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[34]  Robert Wille,et al.  Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks , 2017, 2017 IEEE International Conference on Computer Design (ICCD).

[35]  Robert Wille,et al.  BDD-based synthesis of reversible logic for large functions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[36]  William C. Athas,et al.  Reversible logic issues in adiabatic CMOS , 1994, Proceedings Workshop on Physics and Computation. PhysComp '94.