Majority-Based Spin-CMOS Primitives for Approximate Computing
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[1] Yi Gang,et al. A High-Reliability, Low-Power Magnetic Full Adder , 2011, IEEE Transactions on Magnetics.
[2] Fabrizio Lombardi,et al. A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits , 2017, ACM J. Emerg. Technol. Comput. Syst..
[3] Mauro Olivieri,et al. Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells , 2014, Microelectron. J..
[4] Yiran Chen,et al. Area and performance co-optimization for domain wall memory in application-specific embedded systems , 2015, DAC.
[5] Weisheng Zhao,et al. Domain Wall Shift Register-Based Reconfigurable Logic , 2011, IEEE Transactions on Magnetics.
[6] Mehdi Kamal,et al. Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[7] Zhaohao Wang,et al. Robust magnetic full-adder with voltage sensing 2T/2MTJ cell , 2015, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15).
[8] Kaushik Roy,et al. System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning , 2009, 2009 IEEE Workshop on Signal Processing Systems.
[9] Younghoon Kim,et al. Designing approximate circuits using clock overgating , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[10] Mostafa Rahimi Azghadi,et al. A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders , 2007, ArXiv.
[11] Gregory K. Wallace,et al. The JPEG still picture compression standard , 1991, CACM.
[12] Deliang Fan. Ultra-low energy reconfigurable spintronic threshold logic gate , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).
[13] Sukumar Nandi,et al. Analysis and Design of Adders for Approximate Computing , 2018, ACM Trans. Embed. Comput. Syst..
[14] Fabrizio Lombardi,et al. A Comparative Review and Evaluation of Approximate Adders , 2015, ACM Great Lakes Symposium on VLSI.
[15] S. Fukami,et al. 20-nm magnetic domain wall motion memory with ultralow-power operation , 2013, 2013 IEEE International Electron Devices Meeting.
[16] Kaushik Roy,et al. Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Fabrizio Lombardi,et al. Design and Analysis of Approximate Compressors for Multiplication , 2015, IEEE Transactions on Computers.
[18] Ronald F. DeMara,et al. Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] Naresh R. Shanbhag,et al. Reliable low-power digital signal processing via reduced precision redundancy , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[20] Mohammad Hossein Moaiyeri,et al. An efficient majority-based compressor for approximate computing in the nano era , 2017, Microsystem Technologies.
[21] Jie Han,et al. Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).
[22] Graham A. Jullien,et al. Performance comparison of quantum-dot cellular automata adders , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[23] Sachin S. Sapatnekar,et al. Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor , 2015, Proceedings of the IEEE.
[24] Fabrizio Lombardi,et al. Design of majority logic based approximate arithmetic circuits , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).
[25] Kaushik Roy,et al. Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic , 2014, IEEE Transactions on Nanotechnology.
[26] Keivan Navi,et al. Towards Approximate Computing with Quantum-Dot Cellular Automata , 2017, J. Low Power Electron..
[27] Yu Wang,et al. RRAM-Based Analog Approximate Computing , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[28] Kaushik Roy,et al. IMPACT: IMPrecise adders for low-power approximate computing , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.
[29] Chip-Hong Chang,et al. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..
[30] Dursun Baran,et al. Energy efficient implementation of parallel CMOS multipliers with improved compressors , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).
[31] Fabrizio Lombardi,et al. New Metrics for the Reliability of Approximate and Probabilistic Adders , 2013, IEEE Transactions on Computers.
[32] Zhaohao Wang,et al. Approximate computing in MOS/spintronic non-volatile full-adder , 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).
[33] Jacques-Olivier Klein,et al. Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction , 2016, IEEE Transactions on Electron Devices.
[34] Paolo Ienne,et al. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.
[35] Xuanyao Fong,et al. KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells , 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.
[36] H. Ohno,et al. Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions , 2008 .
[37] Fabrizio Lombardi,et al. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation , 2016, IEEE Transactions on Computers.
[38] Lirida A. B. Naviner,et al. Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.
[39] R. Demara,et al. A Tunable Majority Gate-Based Full Adder Using Current-Induced Domain Wall Nanomagnets , 2016, IEEE Transactions on Magnetics.
[40] Nader Bagherzadeh,et al. Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[41] Kaushik Roy,et al. Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator , 2009, ISLPED.
[42] K. Sridharan,et al. Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity , 2017, IEEE Transactions on Computers.
[43] Anand Raghunathan,et al. Approximation through logic isolation for the design of quality configurable circuits , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[44] Mircea Vladutiu,et al. Computer Arithmetic , 2012, Springer Berlin Heidelberg.
[45] Kaushik Roy,et al. Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[46] Ronald F. DeMara,et al. Composite spintronic accuracy-configurable adder for low power Digital Signal Processing , 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).