Logic design for on-chip test clock generation - implementation details and impact on delay test quality
暂无分享,去创建一个
Matthias Beck | Xijiang Lin | Olivier Barondeau | Frank Poehl | Ron Press | Martin Kaibel | Frank Poehl | Xijiang Lin | Matthias Beck | Olivier Barondeau | R. Press | Martin Kaibel
[1] John A. Waicukauski,et al. Transition Fault Simulation by Parallel Pattern Single Fault Propagation , 1986, International Test Conference.
[2] T.L. McLaurin,et al. The testability features of the ARM1026EJ microprocessor core , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[3] Dawit Belete,et al. Use of DFT techniques in speed grading a 1 GHz+ microprocessor , 2002, Proceedings. International Test Conference.
[4] Robert C. Aitken,et al. IDDQ and AC scan: the war against unmodelled defects , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[5] Kenneth M. Butler,et al. Scan-based transition fault testing - implementation and low cost test challenges , 2002, Proceedings. International Test Conference.
[6] Minesh B. Amin,et al. Efficient compression and application of deterministic patterns in a logic BIST architecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[7] Xijiang Lin,et al. Test generation for designs with multiple clocks , 2003, DAC '03.
[8] Kenneth M. Butler,et al. A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[9] Siyad C. Ma,et al. Testability features of AMD-K6/sup TM/ microprocessor , 1997, Proceedings International Test Conference 1997.
[10] Nilanjan Mukherjee,et al. Industrial experience with adoption of edt for low-cost test without concessions , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[11] P. Nigh,et al. An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[12] Gordon L. Smith,et al. Model for Delay Faults Based upon Paths , 1985, ITC.
[13] Bruce Long,et al. DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[14] Edward J. McCluskey,et al. Analysis and detection of timing failures in an experimental Test Chip , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[15] Brion L. Keller,et al. OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[16] C. Pyron,et al. DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. , 1999 .
[17] John J. Shedletsky,et al. An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.
[18] Manfred Henftling,et al. Path delay ATPG for standard scan design , 1995, Proceedings of EURO-DAC. European Design Automation Conference.
[19] Kurt Keutzer,et al. Delay-fault test generation and synthesis for testability under a standard scan design methodology , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Nilanjan Mukherjee,et al. Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.
[21] Chris Nappi,et al. Scan vs. functional testing - a comparative effectiveness study on Motorola's MMC2107/sup TM/ , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[22] Teresa L. McLaurin,et al. The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).