A constraint scheme for correcting massive asymmetric magnitude-1 errors in multi-level NVMs

We present a constraint-coding scheme to correct large numbers of asymmetric magnitude-1 errors in multi-level non-volatile memories. The scheme is shown to deliver better correction capability compared to known alternatives, while admitting low-complexity of decoding. Our results include an algebraic formulation of the constraint, necessary and sufficient conditions for correctability, a maximum-likelihood decoder running in complexity linear in the alphabet size, and lower bounds on the probability to correct t errors. Besides the superior rate-correction tradeoff, another advantage of this scheme over standard error-correcting codes is the flexibility to vary the code parameters without significant modifications.

[1]  Onur Mutlu,et al.  Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  J. Kessenich,et al.  Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[3]  Bella Bose,et al.  On L1-distance error control codes , 2011, 2011 IEEE International Symposium on Information Theory Proceedings.

[4]  Jehoshua Bruck,et al.  Codes for Asymmetric Limited-Magnitude Errors With Application to Multilevel Flash Memories , 2010, IEEE Transactions on Information Theory.

[5]  Rudolf Ahlswede,et al.  Unidirectional error control codes and related combinatorial problems , 2002 .

[6]  A. Mohr,et al.  Applications of Chromatic Polynomials Involving Stirling Numbers , 2008 .

[7]  J. H. van Lint,et al.  A Course in Combinatorics: Trees , 2001 .