HIGH VOLTAGE DEVICES FOR STANDARD MOS TECHNOLOGIES - CHARACTERISATION AND MODELLING

Abstract This work reports on the analysis of high voltage lateral devices. Two different architectures, self-aligned LDMOS and non-self-aligned XDMOS are presented and used in this work. For the separation of the physical effects that take place inside the HV devices the intrinsic drain voltage concept (V K ) is proposed. The variation of V K is explained and related to the physical effects inside the device and the charge variation. Through the K point potential, the analysis of the channel and drift resistances is performed function of V G and V D for the whole voltage domain. The several orders of magnitude variation of the resistances is explained by the turning off-on of the intrinsic MOS transistor and also by the depletion of the drift part. The capacitances variation function of the gate voltage, for different drain voltages is discussed in detail taking into account the charge repartition inside the device. It is revealed that the charge transfer between the intrinsic MOSFET and the drift part impacts on the capacitances behaviour resulting in specific peaks on C

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