Bias voltage criteria of gate shielding effect for protecting IGBTs from shoot-through phenomena

Abstract In this paper, we propose the criteria of bias voltage from parasitic capacitance and demonstrate the criteria in an experiment with the present IGBT. The bias voltage criteria are theoretically predicted for the new generation IGBT based on the scaling principle. For safe switching, the required gate voltage bias is predicted to be −1.2 V or less for the present IGBTs and − 6 V or less is required to completely cancel the gate noise voltage. From the IGBT design, the bias voltage of scaling IGBT requires −2 V to completely cancel the gate noise voltage.

[1]  Ichiro Omura,et al.  IGBT scaling principle toward CMOS compatible wafer processes , 2013 .

[2]  Masanori Tsukuda,et al.  Structure oriented compact model for advanced trench IGBTs without fitting parameters for extreme condition: Part II , 2014, Microelectron. Reliab..

[3]  Tamotsu Ninomiya,et al.  Modelling of the shoot-through phenomenon introduced by the next generation IGBT in inverter applications , 2017, Microelectron. Reliab..

[4]  A. Sakai,et al.  On the scaling limit of the Si-IGBTs with very narrow mesa structure , 2016, 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD).

[5]  Masanori Tsukuda,et al.  General-purpose clocked gate driver (CGD) IC with programmable 63-level drivability to reduce Ic overshoot and switching loss of various power transistors , 2016, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC).

[6]  Ichiro Omura,et al.  Structure oriented compact model for advanced trench IGBTs without fitting parameters for extreme condition: Part I , 2011, Microelectron. Reliab..

[7]  I. Omura,et al.  Scaling rule for very shallow trench IGBT toward CMOS process compatibility , 2012, 2012 24th International Symposium on Power Semiconductor Devices and ICs.

[8]  Y. Onozawa,et al.  A 1200 V-class Fin P-body IGBT with ultra-narrow-mesas for low conduction loss , 2016, 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD).

[9]  K. Kakushima,et al.  Experimental verification of a 3D scaling principle for low Vce(sat) IGBT , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).