Energy-efficient Design

Energy efficiency has been a key design constraint for microprocessor development teams since the late 1990s. The fundamental technological issues that have led to this point are quite well understood at this time by industry and academia. Although active (or dynamic) and passive (or standby) components of the net power equation are of concern , in recent years the latter (leakage) aspect of chip power has been escalating at a much faster rate than active power. In fact, as we write, leakage power has almost equaled active power in the total power breakdown of a typical microprocessor. This means that a 100 W chip in today's technology will be burning about 50 W with just power on and no program running! And, by the way, the highest-performance, multicore, server-class processors are already close to 200 W in maximum power consumption! This equates to power densities that are pretty much at the very edge of air-cooled systems. So, without investing in liquid cooled systems and their corresponding packaging (at significantly higher cost), microprocessors at the high end, targeted for traditional air-cooled server boxes, are pretty much at the end of the road, without a major paradigm shift in design and/or packaging technology. In fact, such a basic paradigm shift has been in the works for a few years, with the introduction of IBM's dual-core Power4 chip in 2000, for example. The industry in general has recently made a clear shift toward lower frequency, multicore architectures for general purpose high-performance microprocessors. Intel, AMD, and Sun Microsystems have all announced future product roadmaps that embrace the multicore paradigm. Although such a shift has enabled design groups to keep going for a little while, the need for building power efficiency into the chip's noncore components continues unabated. Also, we recently have witnessed a trend toward finer levels of clock gating in all designs, and the increasing use of power-gated modes to reduce leakage. Academic research in low-power design techniques have evolved from lower-level issues related to the underlying device and circuit technologies to higher-level knobs available in the microarchitecture, architecture, and even the application and software layers. In addition to the established International Symposium on Low Power Electronic Design (ISLPED), other smaller conferences and workshops have emerged to highlight the latest research—espe-cially at the architecture and design levels. That's why IEEE Micro, in putting together a special issue on this important theme, decided to …