Design of monolithic circuit chips
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The influence of semiconductor chip design on the logic partitioning of a computer is discussed and some design rules are given. A chip size of 60 × 60 mils with 24 terminals and 168 components was shown to be optimum. RF-sputtered quartz insulation was used for multilevel wiring and a hermetic seal. Using a master chip technique, a 9-part-number logic set was successfully fabricated. Propagation delays for the circuits were 2.5 to 3 nsec.
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