Effects of analog multiplier offsets on on-chip learning
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[1] Takashi Morie,et al. An all-analog expandable neural network LSI with on-chip backpropagation learning , 1994, IEEE J. Solid State Circuits.
[2] Soo-Young Lee,et al. Subthreshold MOS implementation of neural networks with on-chip error backpropagation learning , 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).
[3] Howard C. Card,et al. Tolerance to analog hardware of on-chip learning in backpropagation networks , 1995, IEEE Trans. Neural Networks.
[4] Alan F. Murray,et al. Synaptic weight noise during multilayer perceptron training: fault tolerance and training improvements , 1993, IEEE Trans. Neural Networks.