Interdependencies of Degradation Effects and Their Impact on Computing

Editor’s note: Process variations, aging and wearout, are nonidealities that lead to suboptimal system performance and increased power. In order to understand the effects of these degradation effects, until now, researchers have investigated them thoroughly, but separately from each other. What this article shows is that process variations and wearout are not independent from each other and they need to be considered together. The article shows designers how they can sometimes take advantage of these interdependencies to safely reduce design margins, while in other cases, it is possible that the interdependencies conspire to amplify the effect of the degradation effects in catastrophic ways. —Mircea Stan, University of Virginia

[1]  Jörg Henkel,et al.  Reliability-aware design to suppress aging , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[2]  A. Asenov Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[3]  Jeffrey T. Draper,et al.  Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[4]  Stilianos Siskos,et al.  Comparison between BSIM4.X and HSPICE flicker noise models in NMOS and PMOS transistors in all operating regions , 2007, Microelectron. Reliab..

[5]  Guido Groeseneken,et al.  Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack , 2010 .

[6]  Jörg Henkel,et al.  Towards interdependencies of aging mechanisms , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[7]  Jörg Henkel,et al.  Connecting the physical and application level towards grasping aging effects , 2015, 2015 IEEE International Reliability Physics Symposium.

[8]  Xiaojun Li,et al.  Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation , 2008, IEEE Transactions on Device and Materials Reliability.

[9]  Ali M. Niknejad,et al.  BSIM compact MOSFET models for SPICE simulation , 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

[10]  M. Alam,et al.  A Comparative Study of Different Physics-Based NBTI Models , 2013, IEEE Transactions on Electron Devices.

[11]  Muhammad Shafique,et al.  The EDA challenges in the dark silicon era , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[12]  D. Frank,et al.  Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm , 2006, 2009 Symposium on VLSI Technology.

[13]  K. Takeuchi,et al.  New analysis methods for comprehensive understanding of Random Telegraph Noise , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[14]  Tibor Grasser,et al.  Circuit simulation of workload-dependent RTN and BTI based on trap kinetics , 2014, Microelectron. Reliab..

[15]  Jörg Henkel,et al.  Aging-aware voltage scaling , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).