A performance and routability-driven router for FPGAs considering path delays

This paper presents a new performance and routability driven router for symmetrical array based field programmable gate arrays (FPGAs). The objectives of our proposed routing algorithm are two-fold: (1) improving the routability of the design (i.e., minimizing the maximum required routing channel density) and (2) improving the overall performance of the design (i.e., minimizing the overall path delay). Initially, nets are routed sequentially according to their criticalities and routabilities. The nets/paths violating the routing-resource and timing constraints are then resolved iteratively by a rip-up-and-rerouter, which is guided by a simulated evolution based optimization technique. The proposed algorithm considers the path delays and routability throughout the entire routing process. Experimental results show that our router can significantly improve routability and reduce delay over many existing routing algorithms.

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