Simulation-Based Verification Techniques for System-Level Designs

This chapter discusses the various aspects of simulation-based verification for high-level hardware designs. Simulation-based verification is currently the most widely used verification technique in the industry. With increasing design sizes, writing the simulation test-bench and ensuring the quality of those tests in verifying the complete design will be a huge challenge in the multibillion-transistor designs of the future. The different types of simulations possible at various levels of design abstraction are examined. In the simulation method, a set of simulation models is used in some electronic design automation (EDA) tool that exercises the implementation with a series of input simulation patterns. The output of the simulation is captured and examined for conformity with the output of the specification. The various core algorithms used in commercial simulation tools are elaborated and the various drawbacks and pitfalls of simulation-based verification are highlighted. Some techniques to address each of those drawbacks are discussed in detail. Various automation techniques and tools that are being used to make the tedious task of test-bench generation easier are also discussed. These techniques, coupled with model-driven test generation and higher levels of design abstraction, can be used to make this verification technique scale to multibillion-transistor designs of the future. The chapter concludes with an industrial case study that used simulation-based verification for verifying the design of a 10 GB Ethernet switch chip.