TImestamp-based Selective Cache Allocation

The behavior of the memory hierarchy is key to high performance in today’s GHz microprocessors. The cache level closest to the processor is limited in size and associativity in order to match the short cycle time of the CPU. Even though only data objects soon reused again will benefit from the small cache, all accessed data objects are normally allocated in the cache.

[1]  Gary S. Tyson,et al.  Utilizing reuse information in data cache management , 1998, ICS '98.

[2]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[3]  Vikas Agarwal,et al.  Clock rate versus IPC: the end of the road for conventional microarchitectures , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[4]  W. H. Wang,et al.  Organization and performance of a two-level virtual-real cache hierarchy , 1989, ISCA '89.

[5]  Laszlo A. Belady,et al.  A Study of Replacement Algorithms for Virtual-Storage Computer , 1966, IBM Syst. J..

[6]  Norman P. Jouppi,et al.  Improving direct-mapped cache performance by the addition of a small fully-associative cache and pre , 1990, ISCA 1990.

[7]  Scott McFarling.  Cache replacement with dynamic exclusion , 1992, ISCA '92.

[8]  Wen-mei W. Hwu,et al.  Run-time adaptive cache management , 1998, Proceedings of the Thirty-First Hawaii International Conference on System Sciences.

[9]  Ken Chan,et al.  PA7200: a PA-RISC processor with integrated high performance MP bus interface , 1994, Proceedings of COMPCON '94.

[10]  Antonio Gonzalez,et al.  A data cache with multiple caching strategies tuned to different types of locality , 1995, International Conference on Supercomputing.

[11]  Wen-mei W. Hwu,et al.  Run-time Adaptive Cache Hierarchy Via Reference Analysis , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[12]  Gary S. Tyson,et al.  A modified approach to data cache management , 1995, MICRO 1995.

[13]  Wen-mei W. Hwu,et al.  Run-time Adaptive Cache Hierarchy Via Reference Analysis , 1997, ISCA 1997.

[14]  Håkan Grahn,et al.  SimICS/Sun4m: A Virtual Workstation , 1998, USENIX Annual Technical Conference.

[15]  Antonio González,et al.  A locality sensitive multi-module cache with explicit management , 1999, ICS '99.

[16]  Wen-mei W. Hwu,et al.  Run-Time Cache Bypassing , 1999, IEEE Trans. Computers.

[17]  Santosh G. Abraham,et al.  Efficient simulation of caches under optimal replacement with applications to miss characterization , 1993, SIGMETRICS '93.

[18]  Alan Jay Smith,et al.  Aspects of cache memory and instruction buffer performance , 1987 .

[19]  Chris Wilkerson,et al.  Locality vs. criticality , 2001, ISCA 2001.

[20]  Nancy Warter-Perez,et al.  Modulo scheduling with multiple initiation intervals , 1995, MICRO 1995.

[21]  John Flynn,et al.  Adapting the SPEC 2000 benchmark suite for simulation-based computer architecture research , 2001 .

[22]  Walid A. Najjar,et al.  Evaluation of a Split Scalar/Array Cache Architecture , 1999 .

[23]  Edward S. Davidson,et al.  Reducing conflicts in direct-mapped caches with a temporality-based design , 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.