Multiprocessor-on-a-chip is becoming possible due to progress in semiconductor technologies. In the multiprocessor, the threaded parallel processing requires decreasing the overhead of interthread communication and synchronization. We propose the tagged communication and synchronization memory with the access counter using CAM (TCSM) which supports a high-speed mechanism for the mutual exclusion, the condition synchronization, the barrier synchronization, and the multicasting between the threads. TCSM allocates its entries dynamically and ensures the producer–consumer synchronization by valid/invalid state in the access count. The execution environment of the threads is protected because the tag of TCSM is used for identifying both the task which threads belong to and the storage used by threads. The MTA/TCSM multichip multiprocessor system has been developed to evaluate the multiprocessor-on-a-chip including TCSM. As a result of the evaluation on MTA/TCSM, the overhead of interthread synchronization and communication using TCSM is lower than using the conventional shared memory. © 2001 Scripta Technica, Syst Comp Jpn, 32(4): 1–13, 2001
[1]
William J. Dally,et al.
The Named-State Register File: implementation and performance
,
1995,
Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.
[2]
Kunle Olukotun,et al.
Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
,
1997
.
[3]
Kunle Olukotun,et al.
The case for a single-chip multiprocessor
,
1996,
ASPLOS VII.
[4]
Kunle Olukotun,et al.
Data speculation support for a chip multiprocessor
,
1998,
ASPLOS VIII.
[5]
Todd C. Mowry,et al.
The potential for using thread-level data speculation to facilitate automatic parallelization
,
1998,
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture.
[6]
B J Smith,et al.
A pipelined, shared resource MIMD computer
,
1986
.