Large Scale Integration - an Appraisal

Publisher Summary This chapter discusses the mainstream developments of large scale integration (LSI) and establishes future trends relative to commercial digital computers. Large–scale integration provides a natural implementation for fast scratch pads and buffers and a long–awaited metal–oxide semiconductor (MOS) desk calculator, which is believed to be in an initial delivery stage. The pros and cons of a number of retrieval systems, both with and without indexing are examined. Present–day computers are potentially very efficient for problems that can be formulated well, but they are rather clumsy in heuristic problem solving. Future advances in computer applications demand a broader based familiarity and more comprehensive skill with the full complement of tools at disposal and not just an ability to write isolated digital computer software. The device fabrication, packaging, economic considerations, interconnection strategies, and LSI memories are also discussed. Many of the software-systems problems that exist today are related t o the hardware issues, and must be resolved by separate considerations. The promise held by LSI is that in some as-yet-undeveloped manner its exploitation may help in the resolution of the real problems.

[1]  Sundaram Seshu,et al.  The Diagnosis of Asynchronous Sequential Switching Systems , 1962, IRE Trans. Electron. Comput..

[2]  Michael J. Flynn.  A prospectus on integrated electronics and computer architecture , 1966, AFIPS '66 (Fall).

[3]  D. Murphy.  High-speed non-saturating switching circuits using a novel coupling technique , 1962 .

[4]  R. Dunn,et al.  Active memory design using discretionary wiring for LSI , 1967 .

[5]  M. P. Lepselter.  Beam-lead technology , 1966 .

[6]  J. W. Lathrop,et al.  Semiconductor-network technology—1964 , 1964 .

[7]  Albert B. Tonik.  Development of executive routines, both hardware and software , 1967, AFIPS '67 (Fall).

[8]  R. A. Henle,et al.  Integrated computer circuits—Past, present, and future , 1966 .

[9]  Peter Pleshko,et al.  An Investigation of the Potential of MOS Transistor Memories , 1966, IEEE Trans. Electron. Comput..

[10]  Robert S. Schwartz,et al.  Solid Logic Technology: Versatile, high-performance microelectronics , 1964, IBM J. Res. Dev..

[11]  Klim Maling,et al.  A Computer Organization and Programming System for Automated Maintenance , 1963, IEEE Trans. Electron. Comput..

[12]  B. Murphy,et al.  Transistor-transistor logic with high packing density and optimum performance at high inverse gain , 1968 .

[13]  Bradford Dunham,et al.  The Multipurpose Bias Device - Part I: The Commutator Transistor , 1957, IBM J. Res. Dev..

[14]  D. E. Brewer,et al.  Low power computer memory system , 1967, AFIPS '67 (Fall).

[15]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[16]  Robert A. Short,et al.  CELLULAR ARRAYS FOR LOGIC AND STORAGE. , 1966 .

[17]  J. E. Iwersen,et al.  New implementation of bipolar semiconductor memory , 1967 .

[18]  C. Thornton.  LSI subsystems assembled by the silicon water-chip technique , 1968 .

[19]  Linder Charlie Hobbs.  Effects of large arrays on machine organization and hardware/software tradeoffs , 1966, AFIPS '66 (Fall).

[20]  M. DavisE.,et al.  Solid logic technology , 1964 .

[21]  S. Sze,et al.  A floating gate and its application to memory devices , 1967 .

[22]  O. Wing,et al.  Computer Recognition and Extraction of Planar Graphs from the Incidence Matrix , 1966 .

[23]  Douglas B. Armstrong,et al.  On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets , 1966, IEEE Trans. Electron. Comput..

[24]  D. Kahng.  Semipermanent memory using capacitor charge storage and IGFET read-out , 1967 .

[25]  D. Middleton,et al.  The Multipurpose Bias Device - Part II: The Efficiency of Logical Elements , 1959, IBM J. Res. Dev..

[26]  G. Moore,et al.  The M0S transistor as an individual device and in integrated arrays , 1965 .

[27]  Erich Bloch,et al.  The engineering design of the stretch computer , 1959, IRE-AIEE-ACM '59 (Eastern).

[28]  David H. Chung,et al.  Design of ACP Resistor-Coupled Switching Circuits , 1963, IBM J. Res. Dev..

[29]  J. L. Langdon,et al.  Design of monolithic circuit chips , 1966 .

[30]  Ivor Catt,et al.  A high-speed integrated circuit scratchpad memory , 1966, AFIPS '66 (Fall).

[31]  Robert C. Minnick,et al.  A Survey of Microcellular Research , 1967, JACM.

[32]  Harold S. Stone,et al.  PROPERTIES OF CELLULAR ARRAYS FOR LOGIC AND STORAGE. , 1967 .

[33]  W. R. Smith,et al.  Integrated complementary transistor nanosecond logic , 1964 .

[34]  R. F. Sechler,et al.  ASLT circuit design , 1967 .

[35]  R. M. Warner.  Comparing MOS and bipolar integrated circuits , 1967, IEEE Spectrum.

[36]  A. W. Lo.  A comprehensive view of digital integrated electronic circuits , 1964 .