On algorithmic rate-coded AER generation

This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate on rate-coded AER. The problem is addressed as an algorithmic problem, in which different methods are proposed, implemented and tested through software algorithms. The proposed algorithms are comparatively evaluated according to different criteria. Emphasis is put on the potential of such algorithms for a) doing the frame-based to event-based representation in real time, and b) that the resulting event streams resemble as much as possible those generated naturally by rate-coded address-event VLSI chips, such as silicon AER retinae. It is found that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips. On the other hand, sophisticated algorithms that yield better event distributions are not efficient for real time operations. The methods based on linear-feedback-shift-register (LFSR) pseudorandom number generation is a good compromise, which is feasible for real time and yield reasonably well distributed events in time. Our software experiments, on a 1.6-GHz Pentium IV, show that at 50% AER bus load the proposed algorithms require between 0.011 and 1.14 ms per 8 bit-pixel per frame. One of the proposed LFSR methods is implemented in real time hardware using a prototyping board that includes a VirtexE 300 FPGA. The demonstration hardware is capable of transforming frames of 64times64 pixels of 8-bit depth at a frame rate of 25 frames per second, producing spike events at a peak rate of 107events per second

[1]  Kwabena Boahen,et al.  The Retinomorphic Approach: Pixel-Parallel Adaptive Amplification, Filtering, and Quantization , 1997 .

[2]  G. Shepherd.  The Synaptic Organization of the Brain , 1979 .

[3]  Alejandro Linares-Barranco,et al.  Synthetic generation of address-events for real-time image processing , 2003, EFTA 2003. 2003 IEEE Conference on Emerging Technologies and Factory Automation. Proceedings (Cat. No.03TH8696).

[4]  T. Sacktor.  The Synaptic Organization of the Brain (3rd Ed.) , 1991 .

[5]  Alyssa B. Apsel,et al.  Analysis of data reconstruction efficiency using stochastic encoding and an integrating receiver , 2001 .

[6]  T R Crimmins,et al.  Geometric filter for speckle reduction. , 1985, Applied optics.

[7]  T.S. Lande,et al.  A VLSI communication architecture for stochastically pulse-encoded analog signals , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[8]  T.S. Lande,et al.  An analog approach to "neuromorphic" communication , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[9]  Eric A. Vittoz,et al.  A communication architecture tailored for analog VLSI artificial neural networks: intrinsic performance and limitations , 1994, IEEE Trans. Neural Networks.

[10]  Ph. Hafliger.  Asynchronous event redirecting in bio-inspired communication , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[11]  J. Lee,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[12]  Eric A. Vittoz,et al.  A 12-transistor PFM demodulator for analog neural networks communication , 1995, IEEE Trans. Neural Networks.

[13]  Moshe Abeles,et al.  Corticonics: Neural Circuits of Cerebral Cortex , 1991 .

[14]  Eric A. Vittoz,et al.  A communication scheme for analog VLSI perceptive systems , 1995 .

[15]  Eugenio Culurciello,et al.  16/spl times/16 pixel silicon on sapphire CMOS digital pixel photosensor array , 2004 .

[16]  Péter Érdi,et al.  Theta-modulated feedforward network generates rate and phase coded firing in the entorhino-hippocampal system , 2004, IEEE Transactions on Neural Networks.

[17]  Misha A. Mahowald,et al.  An Analog VLSI System for Stereoscopic Vision , 1994 .

[18]  W. D. Ross,et al.  Visual brain and visual perception: how does the cortex do perceptual grouping? , 1997, Trends in Neurosciences.

[19]  Andreas G. Andreou,et al.  A Contrast Sensitive Silicon Retina with Reciprocal Synapses , 1991, NIPS.

[20]  Kwabena Boahen,et al.  Communicating neuronal ensembles between neuromorphic chips , 1998 .

[21]  Wolfgang Maass,et al.  Spiking Neurons , 1998, NC.

[22]  Denis Fize,et al.  Speed of processing in the human visual system , 1996, Nature.

[23]  John Wawrzynek,et al.  A multi-sender asynchronous extension to the AER protocol , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[24]  Jong-Sen Lee,et al.  A simple speckle smoothing algorithm for synthetic aperture radar images , 1983, IEEE Transactions on Systems, Man, and Cybernetics.

[25]  Rahul Sarpeshkar,et al.  Pulse-Based Analog VLSI Velocity Sensors , 1997 .

[26]  E. Culurciello,et al.  A biomorphic digital image sensor , 2003, IEEE J. Solid State Circuits.

[27]  Kwabena Boahen,et al.  Point-to-point connectivity between neuromorphic chips using address events , 2000 .

[28]  Bernabé Linares-Barranco,et al.  An arbitrary kernel convolution AER-transceiver chip for real-time image filtering , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[29]  E. Vittoz.  Present and Future Industrial Applications of Bio-Inspired VLSI Systems , 2002 .

[30]  Gert Cauwenberghs,et al.  Analog VLSI spiking neural network with address domain probabilistic synapses , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[31]  Eugene M. Izhikevich,et al.  Which model to use for cortical spiking neurons? , 2004, IEEE Transactions on Neural Networks.

[32]  Stephen Grossberg,et al.  A neural network for enhancing boundaries and surfaces in synthetic aperture radar images , 1999, Neural Networks.

[33]  A. Bruce Carlson,et al.  Communication systems: an introduction to signals and noise in electrical communication , 1975 .

[34]  Kwabena Boahen,et al.  Space-rate coding in an adaptive silicon neuron , 2001, Neural Networks.

[35]  Eric A. Vittoz,et al.  An integrated cortical layer for orientation enhancement , 1997 .

[36]  Massimo A. Sivilotti,et al.  Wiring considerations in analog VLSI systems, with application to field-programmable networks , 1992 .

[37]  Andreas G. Andreou,et al.  Asynchronous sampling of 2D arrays using winner-takes-all arbitration , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[38]  Rodney J. Douglas,et al.  A pulse-coded communications infrastructure for neuromorphic systems , 1999 .

[39]  R.M. Gray,et al.  Communication systems: An introduction to signals and noise in electrical communication , 1976, Proceedings of the IEEE.

[40]  Andreas G. Andreou,et al.  AER image filtering architecture for vision-processing systems , 1999 .

[41]  Simon J. Thorpe,et al.  Coding static natural images using spiking event times: do neurons Cooperate? , 2004, IEEE Transactions on Neural Networks.

[42]  Kwabena Boahen,et al.  A throughput-on-demand address-event transmitter for neuromorphic chips , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

[43]  Kwabena Boahen.  Retinomorphic vision systems , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[44]  A. Sedra.  Microelectronic circuits , 1982 .

[45]  Bertram E. Shi,et al.  An ON-OFF orientation selective address event representation image transceiver chip , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[46]  J Szentagothai,et al.  [Neuronal circuits of the cerebral cortex]. , 1970, Bulletin de l'Academie royale de medecine de Belgique.

[47]  Shih-Chii Liu,et al.  Temporal coding in a silicon network of integrate-and-fire neurons , 2004, IEEE Transactions on Neural Networks.

[48]  John Wawrzynek,et al.  Silicon Auditory Processors as Computer Peripherals , 1992, NIPS.

[49]  Hu Chuan-Gan,et al.  On The Shift Register Sequences , 2004 .

[50]  Wolfgang Maass,et al.  A Model for Fast Analog Computation Based on Unreliable Synapses , 2000, Neural Computation.

[51]  Tor Sverre Lande,et al.  Neuromorphic systems engineering: neural networks in silicon , 1998 .

[52]  Stephen Grossberg,et al.  Synthetic aperture radar processing by a multiple scale neural system for boundary and surface representation , 1995, Neural Networks.