Thermal constraints for BBL placement

Trends in microelectronic design go toward increased component integrated density and higher power consumption. Thermal management has had a more prominent role in recent years. Therefore, an accurate thermal model was needed to develop a new placement algorithm designed to consider both minimization of chip area and thermal evenness. Simulated annealing was employed in our algorithm. The experimental results show that the thermal distribution was even and the temperature of the "hot spots" decreased greatly in the chip.