A time optimized test scheduling method under power constraint for NoC

The reuse of on-chip network as a test access mechanism has been proposed to test NoC-Based system recently.However,the test scheduling problem becomes very complex with limited on-chip resources such as channel.An optimized test scheduling method was proposed,which considers both test time and test power.With the premise of reducing the overall test time of all the cores,the location of input/output pairs and the optimized sequence of IP core scheduling during a test were selected according to the minimum cost of all cores.Experimental results show a decrease in test time and overall cost,and an increase in the efficiency during an NoC parallel tests.