论文信息 - A 5.4mW 2-Channel Time-Interleaved Multi-bit /spl Delta//spl Sigma/ Modulator with 80dB SNR and 85dB DR for ADSL

A 5.4mW 2-Channel Time-Interleaved Multi-bit /spl Delta//spl Sigma/ Modulator with 80dB SNR and 85dB DR for ADSL

A 2nd-order DeltaSigma modulator that obtains low power consumption by 2-channel time-interleaving is described. The main channel requires 2 opamps whereas the second channel does not use any active elements. This structure is robust to channel mismatches and uses a simple clocking scheme. The circuit is integrated in a 0.18mum CMOS process and occupies an active area of 1.1mm2

Franco Maloberti | Sunwoo Kwon | Kye-Shin Lee

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