An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping

In this paper, we present an optimized design flow to map Register-Transfer-Level (RTL) netlists onto multiple-FPGA architectures. Our FPGA-dedicated method fully exploits design structure by letting the basic design steps technology mapping, hierarchical partitioning, floorplanning and signal flow driven placement, interact. This efficiently reduces runtime and yields design implementations of higher performance and better resource utilization than published before.

[1]  C. L. Liu,et al.  Area minimization for floorplans , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Erich Barke,et al.  A Universal CLA Adder Generator for SRAM-Based FPGAs , 1996, FPL.

[3]  Martin D. F. Wong,et al.  An enhanced bottom-up algorithm for floorplan design , 1989, Integr..

[4]  Wen-Jong Fang,et al.  A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations , 1996, Proceedings of International Conference on Computer Aided Design.

[5]  Dinesh Bhatia,et al.  Performance driven floorplanning for FPGA based designs , 1997, FPGA '97.

[6]  Clive ″Max″ Maxfield.  Library of Parameterized Modules , 1998 .

[7]  Nikil D. Dutt,et al.  High-level library mapping for arithmetic components , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Dana S. Richards,et al.  Distributed genetic algorithms for the floorplan design problem , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Joseph Varghese,et al.  An efficient logic emulation system , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[11]  Rajeev Murgai,et al.  Improved logic synthesis algorithms for table look up architectures , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[12]  Klaus Eckl,et al.  A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs , 1996, DAC '96.

[13]  Jonathan Rose,et al.  Chortle-crf: fast technology mapping for lookup table-based FPGAs , 1991, 28th ACM/IEEE Design Automation Conference.

[14]  Laura A. Sanchis,et al.  Multiple-Way Network Partitioning , 1989, IEEE Trans. Computers.

[15]  Jason Cong,et al.  A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design , 1993, 30th ACM/IEEE Design Automation Conference.

[16]  Erich Barke,et al.  A universal Pezaris array multiplier generator for SRAM-based FPGAs , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[17]  Maurizio Rebaudengo,et al.  GALLO: a genetic algorithm for floorplan area optimization , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Jonathan Rose,et al.  The Transmogrifier-2: a 1 million gate rapid prototyping system , 1997, FPGA '97.

[19]  Erich Barke,et al.  Hierarchical partitioning , 1996, Proceedings of International Conference on Computer Aided Design.

[20]  Gabriele Saucier,et al.  Synthesis and floorplanning for large hierarchical FPGAs , 1997, FPGA '97.

[21]  Erich Barke,et al.  Circuit partitioning using high level design information , 1996 .

[22]  Joseph Varghese,et al.  An efficient logic emulation system , 1993, IEEE Trans. Very Large Scale Integr. Syst..