Analysis oftheFinFETparasitics forimproved RFperformances

FinFETarchitecture results inhighlevel of parasitics thatoffset theperformance gainthat canbe achieved through gatelength scaling. Inthis work, we investigate technological solutions bothattheprocess integration and layoutlevels to alleviate these limitations. Layout guidelines arederived toimprove theRFperformance. Foranoptimized layout folding, experiments indicate 15%gaininfT.