Color space conversion for MPEG decoding on FPGA-augmented TriMedia processor

A case study on color space conversion (CSC) for MPEG decoding, carried out on the FPGA-augmented TriMedia processor is presented. That is, a transform from Y'CbCr color space to R'G'B' color space is addressed. First, we outline the extension of TriMedia architecture consisting of FPGA-based reconfigurable functional units (RFU) and associated instructions. Then we analyse a CSC (RFU-specific) instruction which can process four pixels per call, and propose a scheme to implement the CSC operation on RFU(s). When mapped on an ACEX EP1K100 FPGA, the proposed CSC exhibits a latency of 10 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 57% of the device. By configuring the CSC facility on the RFU(s) at application load-time, color space conversion can be computed on FPGA-augmented TriMedia with 40% speed-up over the standard TriMedia.

[1]  Joan L. Mitchell,et al.  MPEG Video Compression Standard , 1996, Springer US.

[2]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[3]  S. Vassiliadis,et al.  IDCT Implementation on an FPGA-Augmented TriMedia , 2001 .

[4]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[5]  Stamatis Vassiliadis,et al.  An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[6]  Stamatis Vassiliadis,et al.  MPEG macroblock parsing and pel reconstruction on an FPGA-augmented TriMedia processor , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[7]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[8]  H. P. E. Vranken,et al.  TriMedia CPU 64 Architecture , .

[9]  Stamatis Vassiliadis,et al.  MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64 , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[10]  Arun N. Netravali,et al.  Digital Video: An introduction to MPEG-2 , 1996 .

[11]  Lex Augusteijn,et al.  Instruction Scheduling for TriMedia , 1999, J. Instr. Level Parallelism.

[12]  Charles A. Poynton,et al.  A technical introduction to digital video , 1996 .

[13]  Andy D. Pimentel,et al.  TriMedia CPU64 architecture , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[14]  P. Vaidyanathan Multirate Systems And Filter Banks , 1992 .