Efficient algorithms and architectures for turbo and ldpc based systems

Channel codes based on iterative decoding such as Turbo codes and low density parity check (LDPC) codes have performance that is close to the Shannon limit. The superior performance of these codes, however, comes with an increase in implementation complexity, decoding latency, and memory overhead. The work presented in this dissertation addresses several issues in the efficient hardware (VLSI and DSP processor based) implementation of Turbo and LDPC coders. In the design of high throughput Turbo decoders, multiple windows are processed simultaneously by using the sliding window (SW) approach. An optimal memory sub-banking scheme that supports the SW approach is presented. Next, energy-scalable Turbo code decoding algorithms for a Space-Time coded system are derived. The algorithms are evaluated in terms of BER performance and energy consumption. This enables us to select the appropriate algorithm based on different energy and quality requirement. A high throughput architecture for the LDPC decoder is also presented. The throughput is doubled by designing circulant matrix based LDPC code that has more than one shifted identity matrix in the sub-matrices. Finally, a general design flow for the architecture-aware LDPC code/decoder co-design is proposed. The architectural features of a DSP processor based software define radio (SDR) platform are formally characterized and turned into constraints in the code design stage. Two case studies are conducted, namely, interconnection-aware code design and memory-traffic aware code design. The results show that in both cases, the architecture-aware code can be decoded with much higher efficiency in the target architecture compared with the random generated counterpart without performance loss.