A practical fault induction attack against an FPGA implementation of AES cryptosystem

Fault-based side channel cryptanalysis is a very effective cryptanalytic technique against symmetric and asymmetric encryption algorithms. Attackers can induce errors during the encryption or decryption process in order to collect information concerning secret information, such as cryptographic keys. In recent years, the security of the Advanced Encryption Standard (AES) against fault analysis attacks has received considerable attention. While FPGAs are becoming increasingly popular for cryptographic applications, there are only few articles that assess their vulnerability to such attacks only a small number of experiments can be found in the literature on the actual possibility to apply such attacks to FPGAs. The purpose of this paper is to describe a practical and successful implementation of the attack and to provide strong evidence that fault induction is a serious threat against realizations of the AESon FPGAs without effective countermeasure. The results obtained in this paper can serve to design a more secure FPGA implementation of the AES.