Design and Implementation of Hardware Fusion Technology for Super Sink Node

For the shortage of the traditional sink nodes of WSNs in refining and compressing the uplink data, a new method is proposed to design and implement a super sink node with the hardware fusion technology. This method adopts FPGA as the platform of the node and applies BP neural networks with systolic array structure, map arithmetic, stream line and nonlinear activation functions to achieve the hardware fusion of uplink data. The experiment shows that the proposed method has decreased the total amount of data, reduced the transmission bandwidth and improved the performance of real-time transmission.

[1]  Li Jian-Zhong,et al.  Concepts, Issues and Advance of Sensor Networks and Data Management of Sensor Networks , 2003 .

[2]  Michael J. Schulte,et al.  The Symmetric Table Addition Method for Accurate Function Approximation , 1999, J. VLSI Signal Process..

[3]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[4]  Michael J. Schulte,et al.  Accurate function approximations by symmetric table lookup and addition , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[5]  Wang Zhensong Realization of BP Algorithm in FPGA Based on Systolic Array Architecture , 2006 .

[6]  Wan Yong Neural networks hardware implementation based on FPGA , 2007 .

[7]  S. Y. Kung,et al.  Digital VLSI architectures for neural networks , 1989, IEEE International Symposium on Circuits and Systems,.

[8]  S. Y. Kung,et al.  Parallel architectures for artificial neural nets , 1988, IEEE 1988 International Conference on Neural Networks.

[9]  S. Y. King Parallel architectures for artificial neural nets , 1988, [1988] Proceedings. International Conference on Systolic Arrays.