Physical Design Overview
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[1] Massoud Pedram,et al. Electronic design automation at the turn of the century: accomplishments and vision of the future , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] R. M. Mattheyses,et al. A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.
[3] Malgorzata Marek-Sadowska,et al. Timing driven placement , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[4] Andrew B. Kahng,et al. New spectral methods for ratio cut partitioning and clustering , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] T. Ohtsuki,et al. Layout design and verification , 1986 .
[6] Kamal Chaudhary,et al. RITUAL: a performance driven placement algorithm , 1992 .
[7] Chung-Kuan Cheng,et al. Ratio cut partitioning for hierarchical designs , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] H. J. Kahn. Book and publicationDesign automation of digital systems vol 1: Theory and techniques: Edited by Melvin A. Breuer, Prentice-Hall Inc., New Jersey (1972) £7.50, 420 pp , 1973 .
[9] H. Murata,et al. Rectangle-packing-based module placement , 1995, ICCAD 1995.
[10] Andrew B. Kahng,et al. Multilevel circuit partitioning , 1997, DAC.
[11] Brian W. Kernighan,et al. An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..
[12] Yoji Kajitani,et al. Module packing based on the BSG-structure and IC layout applications , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[13] T. Ohtsuki,et al. Recent advances in VLSI layout , 1990, Proc. IEEE.
[14] Yoji Kajitani,et al. The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization , 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).
[15] Jason Cong,et al. High-performance clock routing based on recursive geometric matching , 1991, 28th ACM/IEEE Design Automation Conference.
[16] Majid Sarrafzadeh,et al. Congestion estimation during top-down placement , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Michael Burstein,et al. Timing Influenced Layout Design , 1985, DAC 1985.
[18] Ernest S. Kuh,et al. VLSI circuit layout : theory and design , 1985 .
[19] Ernest S. Kuh,et al. Proud: a fast sea-of-gates placement algorithm , 1988, DAC '88.
[20] Yici Cai,et al. Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[21] Chung-Kuan Cheng,et al. Module Placement Based on Resistive Network Optimization , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[22] J. Soukup. Circuit layout , 1981, Proceedings of the IEEE.
[23] R. Tsay. Exact zero skew , 1991, ICCAD 1991.
[24] Joseph R. Shinnerl,et al. Multilevel optimization for large-scale circuit placement , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[25] Antoni A. Szepieniec,et al. The Genealogical Approach to the Layout Problem , 1980, 17th Design Automation Conference.
[26] Naveed A. Sherwani,et al. Algorithms for VLSI Physical Design Automation , 1999, Springer US.
[27] C. Y. Lee. An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..
[28] D. F. Wong,et al. Efficient network flow based min-cut balanced partitioning , 1994, ICCAD 1994.
[29] Arvind Srinivasan,et al. Clock routing for high-performance ICs , 1991, DAC '90.
[30] Ronald L. Graham,et al. Revisiting floorplan representations , 2001, ISPD '01.
[31] Majid Sarrafzadeh,et al. Dragon2000: standard-cell placement tool for large industry circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[32] Fred W. Glover,et al. Multilevel cooperative search for the circuit/hypergraphpartitioning problem , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[33] Takeshi Yoshimura,et al. Floorplanning using a tree representation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[34] Majid Sarrafzadeh,et al. An Introduction To VLSI Physical Design , 1996 .
[35] Thomas Lengauer,et al. Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.
[36] G. Sigl,et al. GORDIAN: a new global optimization/rectangle dissection method for cell placement , 1988, ICCAD 1988.
[37] Sung-Woo Hur,et al. Mongrel: hybrid techniques for standard cell placement , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).