Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume

We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells. Relative measures are presented to reflect the gains when controlling a scan cell to a certain value, and guide the scan cell selection. Experimental results on larger IWLS 2005 benchmark circuits show that, to achieve the same fault coverage of the pure launch on capture (LOC) approach, the volume of test data can be reduced to a half on average by replacing only 1% of regular scan cells to enhanced scan cells. The transition delay fault coverage can also be improved using the proposed method with equally low area overhead.

[1]  C. P. Ravikumar,et al.  Local at-speed scan enable generation for transition fault testing using low-cost testers , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Adit D. Singh,et al.  Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing , 2009, 2009 Asian Test Symposium.

[3]  B. I. Devadas,et al.  Design for testability : Using scanpath techniques for path-delay test and measurement , 1991 .

[4]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Ali Keshavarzi,et al.  View from the bottom: nanometer technology AC parametric failures - why, where, and how to detect , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  Irith Pomeranz,et al.  Methods for improving transition delay fault coverage using broadside tests , 2005, IEEE International Conference on Test, 2005..

[7]  Kwang-Ting Cheng,et al.  New challenges in delay testing of nanometer, multigigahertz designs , 2004, IEEE Design & Test of Computers.

[8]  Adit D. Singh,et al.  Achieving high transition delay fault coverage with partial DTSFF scan chains , 2007, 2007 IEEE International Test Conference.

[9]  Adit D. Singh,et al.  Fast test application technique without fast scan clocks , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[10]  Wenlong Wei,et al.  Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns , 2008, 2008 13th European Test Symposium.

[11]  Kaushik Roy,et al.  A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application , 2005, Design, Automation and Test in Europe.

[12]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[14]  Kurt Keutzer,et al.  A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits , 1991, 1991, Proceedings. International Test Conference.

[15]  Jacob Savir,et al.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[16]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[17]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[18]  Akshay Gupta,et al.  Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis , 2006, 2006 IEEE International Test Conference.

[19]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[20]  Xiao Liu,et al.  Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[21]  Xiaoqing Wen,et al.  A Framework of High-quality Transition Fault ATPG for Scan Circuits , 2006, 2006 IEEE International Test Conference.

[22]  Gefu Xu,et al.  Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan , 2007, 16th Asian Test Symposium (ATS 2007).