Low-cost signature test of RF blocks based on envelope response analysis

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

[1]  Gloria Huertas,et al.  Sine-Wave Signal Characterization Using Square-Wave and ΣΔ-Modulation: Application to Mixed-Signal BIST , 2005, J. Electron. Test..

[2]  J. Silva-Martinez,et al.  Built-in Self Test of RF Transceiver SoCs: from Signal Chain to RF Synthesizers , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

[3]  Tejasvi Das,et al.  An ultra-fast, on-chip BiST for RF low noise amplifiers , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[4]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[5]  Alberto Valdes-Garcia,et al.  On-Chip Testing Techniques for RF Wireless Transceivers , 2006, IEEE Design & Test of Computers.

[6]  Abhijit Chatterjee,et al.  A signature test framework for rapid production testing of RF circuits , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Gloria Huertas,et al.  (Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems , 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

[8]  Sule Ozev,et al.  Defect-based RF testing using a new catastrophic fault model , 2005, IEEE International Conference on Test, 2005..

[9]  Sule Ozev,et al.  Diagnosis of the failing component in RF receivers through adaptive full-path measurements , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[10]  Abhijit Chatterjee,et al.  Built-in test of RF components using mapped feature extraction sensors , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[11]  J. Dugundji,et al.  Envelopes and pre-envelopes of real waveforms , 1958, IRE Trans. Inf. Theory.

[12]  Gordon W. Roberts,et al.  On-chip analog signal generation for mixed-signal built-in self-test , 1999 .

[13]  Abhijit Chatterjee,et al.  A system-level alternate test approach for specification test of RF transceivers in loopback mode , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[14]  D. Vazquez,et al.  On-Chip Analog Sinewave Generator with Reduced Circuitry Resources , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[15]  Sumantra Seth,et al.  An integrated linear RF power detector , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[16]  Sangwook Nam,et al.  A novel wide-band envelope detector , 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

[17]  Diego Vázquez,et al.  On-chip characterisation of RF systems based on envelope response analysis , 2010 .

[18]  Abhijit Chatterjee,et al.  Low-cost parametric test and diagnosis of RF systems using multi-tone response envelope detection , 2007, IET Comput. Digit. Tech..

[19]  Bruce C. Kim,et al.  A new low-cost RF built-in self-test measurement for system-on-chip transceivers , 2006, IEEE Transactions on Instrumentation and Measurement.

[20]  Michael S. Heutmaker,et al.  An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan , 1999, IEEE Commun. Mag..

[21]  Tao Zhang,et al.  A translinear RMS detector for embedded test of RF ICs , 2005, IEEE Transactions on Instrumentation and Measurement.