This paper describes a 160 MHz 500 mW StrongARM®! microprocessor designed for low-power, low-cost applications. The chip implements the ARM® V 4 instruction set (II and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 m W to 200 MHz at 2.0 V for less than 900 m W. An on-chip I'LL provides the internal clock based on a 3.68 MHz dock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-flm three-metal CMOS process with 0.35 V thresholds and 0.25 ,Lm effective channel lengths. The chip measures 7.8 mm x 6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package.