PAFLO: a fast standard-cell detailed placement algorithm

In this paper, we present a fast detailed placement algorithm, PAFLO, which inherits the positions of cells given by a global placer and allocates exact position to each cell using local optimization. In our algorithm, we use two techniques to optimize the total wirelength in y and x directions respectively. In y direction, we adopt FM Min-cut to exchange cells in adjacent rows for optimizing total wirelength; while in x direction, we use a technique based on the optimal positions of cells to rearrange the local cells for optimizing total wirelength. Experimental results show, comparing to FAME, PAFLO can produce almost equal results on total wirelength (0.1%) while spending much less amount of time (2.3 /spl times/ speedup).

[1]  Andrew B. Kahng,et al.  Optimization of linear placements for wirelength minimization with free sites , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[2]  Andrew B. Kahng,et al.  Optimal partitioners and end-case placers for standard-cell layout , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Jeff Parkhurst,et al.  SRC physical design top ten problem , 1999, ISPD '99.

[4]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[5]  Kamal Chaudhary,et al.  RITUAL: a performance driven placement algorithm , 1992 .

[6]  Hou Wen Fame:A Fast Detailed Placement Algorithm for Standard\| Cell Layout Based on Mixed Mincut and Enumeration , 2000 .

[7]  Jürgen Koehl,et al.  An analytic net weighting approach for performance optimization in circuit placement , 1991, 28th ACM/IEEE Design Automation Conference.

[8]  Jeff Parkhurst,et al.  SRC Physical Design Top Ten Problems , 1999 .

[9]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[10]  Majid Sarrafzadeh,et al.  Dragon2000: standard-cell placement tool for large industry circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[11]  Andrew B. Kahng,et al.  Optimal partitioners and end-case placers for standard-cell layout , 1999, ISPD '99.

[12]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..