Formal Verification of Globally-Iterated/Locally-Non-Iterated Systems

Abstract Formal Verification of hardware has significantly gained in popularity as an alternative to testing and simulation in hardwaredesign. Recently we introduced a new methodology for verification of non-iterated systems. The technique is based on theinductively defined notion of a series-parallel poset. In this paper we extend the notion of series-parallel posets to allow themodeling of systems involving global iteration. For this class of systems we present a verification algorithm, and discuss itsfoundation._______________________________________________________________________________________________ _____Introduction An iterated system is a system which employs feedback inits own operation or the operation of one or more of itscomponents. Our goal is to provide an approach thatallows us to verify the occurrence of sequences of eventsduring the operation of the system.Examples of iterated systems at the hardware level includethe following:a) At the logic gate level, any sequential circuit (e.g.a flip-flop), which involves feedbackb) At the system level, any system which performsmultiple iterationsc) Various protocols for serial and parallel datacommunication, involving the repeated sendingand receiving of data.Series Parallel Posets:In a recent paper [INB™99] we introduced the notion ofseries-parallel posets for verification of non-iteratedsystems. A partially ordered set (poset) is a set with a reflexive,antisymmetric, and transitive relation defined on the setelements. A Σ