A Tutorial on Hybrid PLL Design for Synchronization in Wireless Receivers ( companion paper to the workshop “ Synchronization and Receiver Structures in Digital Wireless Communications ” )

Coherent reception in digital wireless communications involves generating a local carrier that is in phase with the received carrier, and then using this local carrier in order to demodulate the received signal. Generation of the local carrier is generally done via a Phase Lock Loop (PLL). The receiver also includes a symbol timing synchronization PLL, whose purpose is to determine the optimal time for sampling of the received signal in order to sample each symbol at its peak and thus minimize the error rate. The objective of the workshop entitled “Synchronization and Receiver Structures in Digital Wireless Communications” [1] is to develop a systematic method for the incorporation of digital signal processing theory into the design and implementation of hybrid PLLs used in digital communications. Additionally, the workshop aims to provide an overview of all the important elements in the receiver, their operation, and their interactions. In this companion paper we shall only outline the core material of the workshop while omitting many mathematical derivations and other important content that shall only be presented in the workshop. Nonetheless, an attempt has been made to make this paper self-contained and thus it is hoped that this paper can serve as a useful reference for workshop attendees and for others.