VLSI implementation of greedy-based distributed routing schemes for ad hoc networks

We describe a VLSI implementation based on a FPGA of a new greedy algorithm for approximating minimum set covering in ad hoc wireless network applications. The implementation makes the algorithm suitable for embedded and real-time architectures. The algorithm, while not randomized, is based on a probability distribution that leads the greedy choice. The algorithm has been specifically tailored to run on platforms with minimal computational hardware.

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