A 14-bit 10- mu s subranging A/D converter with S/H

A microprocessor-compatible, 14-bit, 10- mu s subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated. >