Optimizing multipliers for WSI

For arithmetic circuits, it is important to maximize the speed and to minimize the power consumption, which may be accomplished by minimizing the product of the delay and the power consumption. The authors discuss the speed and the number of logic transitions (a measure of power dissipation for static CMOS circuits) of several different parallel multipliers. The circuits are constructed with inverters and two- to four-input AND and OR gates. Extensive simulation is used to evaluate their switching characteristics, and the results of the simulations are used to rank the multipliers on speed, size, and the number of logic transitions.<<ETX>>

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